Systematic VLSI Design and Implementation of Low Power High Speed Up sampler Using Multirate

Paper Presents Systematic VLSI design of Low Power and Area using Multirate digital signal processing system. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is up sampler; FPGA implementation of the same is presented. The FPGA synthesis results are verified and report is presented. In order to build up sampler consisting of Shift register, D F/F and Multiplexer are downloaded on cycloneII FPGA of ALTERA QUARTUS–II platform. The circuit obtained is verified and implemented successfully. Then it is synthesized using 45 nm library in synopsis tool with constraint of low power and area. Reduction of power consumption is important parameter for system.